1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a technology which is effective if applied for accelerating the operation speed of a static type random access memory (as will be abbreviated into the "static RAM").
2. Description of the Prior Art
A semiconductor memory device such as a static RAM or a dynamic RAM composed of MOS transistors (i.e., Metal Oxide Silicon field effect transistors, as abbreviated into MOSFET) is generally composed of the following sense system. Specifically, the data are read by transferring data stored in a memory cell via a pair of complementary data lines or common data lines, to a sense amplifier circuit which detects and amplifies the signal amplitude of the read data. This amplified signal is fed to and is further amplified by an output circuit which, in turn, generates external output data corresponding to the data read from the aforementioned memory cell. The external output data is made available for use outside of the semiconductor chip, formed, e.g., with a static RAM.
An example of a static RAM having a short address access time is exemplified by the static RAM which is composed of bipolar transistors and MOS transistors, such as disclosed in Japanese Patent Laid-Open No. 170090/1985 (corresponding to U.S. Pat. No. 4,713,796). This static RAM utilizes a sense amplifier circuit composed of differentially coupled bipolar transistors so as to shorten the address access time. Thus, the sense system described above is also adopted in the high-speed static RAM which is composed of bipolar transistors and MOS transistors.